An nLDMOS device is a common ESD protection device in high voltages processes. However, traditional nLDMOS devices suffer from latch-up due to inherently strong snapback characteristics. One traditional approach is to stack nLDMOS ESD devices to increase the holding voltage (Vh). However, this approach wastes substrate area, and reduces ESD protection performance.
FIG. 1 schematically illustrates a traditional nLDMOS device that suffers from latch-up due to inherently strong snapback characteristics. As shown, the device in FIG. 1 includes a p-type substrate 101 having a dual voltage n-well (DVNW) region 103, a high voltage p-well (HVPW) region 105 in the DVNW region 103, and a high voltage n-type double diffusion drain (HVNDDD) 107 in the HVPW region 105. Under an ESD condition, for instance, positive zapping from a drain region 109 to a source region 111, a device breakdown or trigger voltage (Vt) is reached, resulting in charges or holes going though HVPW region 105. Once reaching a trigger voltage, for instance point 113, a snapback to a Vh, for instance point 115, results. Point 113 may, for example, represent a Vt of 34 volts (V), and point 115 may represent a Vh of 9 V for a normal operation voltage of 24 V (or 30 V), resulting in a latch-up of the traditional nLDMOS device.
FIG. 2 illustrates characteristics of a traditional nLDMOS device. Once reaching Vt 201, traditional nLDMOS devices will snapback to a Vh 203 that is less than an operating voltage 205. As illustrated in FIG. 2, traditional devices latch-up due to the inherently strong snapback or base push-out characteristic.
A need therefore exists for an improved nLDMOS ESD protection device, having an increased Vh, resulting in non-snapback behavior, and an increased trigger current, and enabling methodology.